The present invention relates to an input buffer circuit.
An input buffer circuit for amplifying an externally inputted signal is provided in a semiconductor memory device or the like. A conventional input buffer circuit has the structure such as shown in FIG. 3. An external input terminal IN is connected to an input terminal of a first inverter IV11 whose output terminal is connected to a node NA. This node NA is connected to an input terminal of a second inverter IV12 whose output terminal is connected to an output terminal OUT of this circuit.
In the second inverter IV12, the gate of a P channel transistor P11 and the gate of an N channel transistor N11 are connected to the nodes NA. The source of the P channel transistor P11 is connected via a resistor R11 to a power source voltage Vcc terminal, and the drain thereof is connected to the drain of the N channel transistor N11 . The source of the N channel transistor N11 is connected via a resistor R12 to a ground potential Vss terminal. The drains of the P and N channel transistors P11 and N 11 are connected in common to the output terminal OUT.
When a signal of logical level "1" is applied to the external input terminal IN, the logical level of the node NA at the output terminal of the first inverter IV11 becomes "0". With the logical level "0" of the node NA, the P channel transistor P11 of the second inverter IV12 turns on and the N channel transistor N11 turns off, so that a signal of logical level "1" is outputted from the output terminal OUT.
Conversely, when a signal of logical level "0" is applied to the external input terminal IN, the logical level of the node NA at the output terminal of the first inverter IV11 becomes "1". With the logical level "1" of the node NA, the P channel transistor P11 turns off and the N channel transistor N11 turns on, so that a signal of logical level "0" is outputted from the output terminal OUT.
When an unsteady signal having an intermediate level between the logical levels "1" and "0" is applied to the external input terminal IN, the level of the node NA at the output terminal of the first inverter IV11 is also unsteady. If the intermediate level of the node NA between the logical levels "1" and "0" is lower than the threshold voltage Vtp of the P channel transistor P11 and higher than the threshold voltage Vth of the N channel transistor N11 , both the transistors turn on. As a result, a signal of unsteady level is outputted from the output terminal OUT.
As discussed above, when a signal of unsteady level is inputted to the external input terminal IN, the serially connected P channel transistor P11 and N channel transistor N11 both turn on. As a result, current flows through the power source voltage Vcc terminal and ground potential Vss terminal, increasing the power consumption more than when a signal of logical level "1" or "0" is inputted.